The present invention relates to power integrity verification for electrical designs. In particular, embodiments of the present invention provide methods, systems, and methodologies to validate electrical characteristics of power distribution systems (PDSs) in electrical (e.g., IC chip) designs. This type of verification can, for example, ensure that each cell and transistor in the design receive sufficient voltage to operate functionally correct.
Some embodiments of the invention provide a methodology, method, and system for multi-level hierarchical, vector-independent dynamic verification of PDS in Systems on Integrated Circuit or Systems-on-a-Chip (hereinafter SoC) with transistor level resolution. Examples of SoC include small electronic devices made out of semiconductor materials which contain various functional components such as memory, digital and analog blocks made out of passive and active electronic devices. Examples of PDS include physical wiring composed of electrical conductive segments providing electrical connection between the pins of a SoC to all active and passive devices on a SoC.
Examples of systems and methods having multi-level hierarchical verification include systems and methods having the ability to validate the PDS for a cell, macro, or block of a SoC, to extract the physical and electrical characteristic of the cell, macro or block, and to generate a model. Such a model is defined as a PDS model. A PDS model can be used for the verification of PDS at the next hierarchy level. The next hierarchy level can be a macro, a block, or the complete SoC. This methodology is called the bottom-up multi-level hierarchical verification.
Other examples for multi-level hierarchical verification include systems and methods having the ability to perform PDS verification at a specific hierarchy level using PDS models and to capture boundary conditions for each component described by a PDS model and used in the hierarchical levels of investigation. The captured boundary conditions can then be used for PDS verification at a lower hierarchical level. This methodology is called the top-down multi-level hierarchical verification.
Dynamic verification of PDS in SoC includes, for example, the capability to calculate the time-dependent voltages and currents for all segments of PDS. Static verification of PDS in SoC includes, for example, the capability to calculate the time-independent (also called average or peak) voltages and currents for all segments of PDS.
Vector-independent dynamic verification of PDS in SoC includes, for example, the capability to calculate the time-dependent power or current consumption of the components of a SoC independent of functional stimuli for the components of a SoC. Transistor level resolution includes, for example, the ability to calculate the time-dependent fluctuations of the voltages at all segments of PDS from the external connections of the SoC (power and ground pins) through all wire segments of PDS to terminals to active and passive semiconductor devices such as transistors and capacitors for all types of components of SoC.
Prior approaches for implementing power distribution analysis all suffer significant functional drawbacks. For example, systems that perform dynamic verification at transistor level require user provided functional stimuli to calculate the time-dependent current consumption. Moreover, systems that perform dynamic verification at transistor or gate level do not allow for multi-level hierarchical PDS verification. Systems that perform dynamic verification at gate level also require either user provided definitions of switching probabilities for each signal net between the components of SoC or user provided functional stimuli for primary inputs of the SoC or the components thereof. Furthermore, vector-independent dynamic verification at gate level does not provide transistor level resolution for PDS verification. In addition, prior approaches also lack the ability to calculate realistic approximation of worst-case time-dependent current consumption for SoC without user specified power constraints. Finally, prior approaches also lack means for sending effective feedback to the users about the electrical characteristic of PDS and decoupling capacitors.
Some embodiments of the present invention overcomes the limitations of prior solutions by enabling dynamic verification at the gate level requiring neither user provided definitions of switching probabilities for each signal net between the components of SoC nor user provided functional stimuli for primary inputs of SoC as well as a statistical approach to determine locally simultaneously switching components and creating worst case voltage fluctuations. Some embodiments of the instant invention are directed to both a dynamic top-down and a dynamic bottom-up multi-level hierarchical PDS verification with transistor level resolution. In addition, some embodiments of the present invention teach a vector-independent dynamic verification at gate level with transistor level resolution for PDS verification and enable the use of static PDS verification techniques to build PDS models for components of SoC and the use of these models for multi-level hierarchical dynamic PDS verification. Furthermore, some embodiments of the instant invention provide a methodology to measure the effectiveness of explicit decoupling capacitors for placement optimization as well as graphical representation. In addition, some embodiments of the present invention teach a methodology to take into account the variation of the electrical circuit behavior due to manufacturing process variations for the vector-independent calculation of current consumption for SoC.
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.